Back-light control circuit of multi-lamps liquid crystal display

ABSTRACT

A multi-lamps LCD back-light control circuit comprises a control unit, an full bridge switch, a resonance network circuit, a voltage transformer, a lamp, and a feedback network. A constant operating frequency and a pulse width modulation (PWM) feedback are used to control the CCFL current. The back-light control circuit is such that a power switch of the full bridge switch outputs a duty cycle that is controlled and changed via a PWM controller of the control unit, while a ground switch of the full bridge switch outputs a constant duty cycle controllable above 50%.

FIELD OF THE INVENTION

The invention relates to a multi-lamps LCD back-light control circuit.More particularly, the invention provides a control circuit that cansimplify the circuitry of dimensionally larger LCD devices.

BACKGROUND OF THE INVENTION

Compared to traditional white thermal lamps, cold cathode fluorescentlamps (CCFL) have many advantages such as higher efficiency and longerservice life. Therefore, an important number of liquid crystal display(LCD) presently uses CCFL as light source. To achieve a stable operationof the CCFL, the power frequency needed is about 30 KHz through 80 KHzwithout the stringed wave from the DC current part while the operatingvoltage is approximately constant. The illumination of the lamp isdetermined according to the tube current there through. The voltageneeded to turn on the lamp is higher than the normal stable operatingvoltage 2 to 2.5 times. The turn on voltage and operating voltage of theCCFL are determined from the size of the CCFL. Traditional 14″, 15″ LCDscreens incorporate CCFL that require a turn-on voltage of about 1400Vrms, and an operating voltage of about 650 Vrms at the highest normalcurrent of 7 mA. To regulate the CCFL, a common control method is theuse of an electrical stabilizer such as a typical fixed frequencyoperation full bridge phase shift converter that can convert directcurrent to alternating current.

As shown in FIG. 1, a typical fixed frequency operation full bridgephase shift converter comprises a resonance inductor 105, a capacitor106 circuit, a lamp 107, NMOS switches 101, 102, 103, 104, and DCcurrent 108. The turn-on or turn-off of NMOS switches 101, 102, 103, 104are respectively controlled via the gale voltages VG1, VG2, VG3, VG4.Typical control signals are four similar constant frequencies with asame duty cycle slightly smaller than 50% and different square waves. Atypical fixed frequency operation full bridge phase shift convertermoves the phase of the control voltage so as to use different sizes ofphase retardations to generate different output powers. FIG. 2A and FIG.2B schematically illustrate the operation time/sequence of a typicalfixed frequency operation full bridge phase shift converter. To preventthe NMOS switches 101, 102 (and 103, 104), directly connected to eachother, to be simultaneously turned off, which causes a power loss, thecontrol signals VG1, VG2 (and VG3, VG4) must maintain a phaseretardation of 180°. The phase retardation of VG1, VG3 in FIG. 2A issmaller than that of FIG. 2B, which generates a higher duty cycle VABand more power outputs.

However, the present use of traditional fixed frequency operation fullbridge phase shift converter in LCD screens presents several problems.Within present LCD devices, the DC voltage provided by the circuit isonly about 10 to 20 volts. The electrical stabilizer of the CCFL of FIG.1 needs a direct voltage of hundreds of volts to operate. Moreover, thisstabilizer uses a NMOS as power switch. As a result, when it is driven,the voltage VG1 (respectively VG2) at the point A (respectively B) mustbe cautiously increased. Additional step-up circuits thus must beincluded within the driving circuits of the NMOSFET power switches 101,104.

SUMMARY OF THE INVENTION

It is therefore a first object of the invention to provide a CCFLcontrol circuit that is adapted to a dimensional increase of the LCDdevices.

It is a second object of the invention to provide a CCFL control circuitthat incorporates a step-up voltage transformer so that the number ofhigh-voltage resistant elements can be reduced within the controlcircuit.

Furthermore, it is third object of the invention to provide a CCFLcontrol circuit that incorporates PMOSFET as power switches so thatadditional step-up circuits are not needed to directly drive theswitches.

Still, it is a fourth object of the invention to provide a CCFL controlcircuit in which the cycle of ground switches is fixed so as to changethe cycle of the power switches, thereby the voltage conversion is moreefficient.

Furthermore, it is a fifth object of the invention to provide a CCFLcontrol circuit in which the cycle of ground switches is fixed so as tochange the cycle of the power switches, thereby most of the circuitcurrent flows through the ground switches. Loss increase due to higherresistivity of PMOS-FET power switches is therefore favorably reduced.

Still, it is a sixth object of the invention to provide a CCFL controlcircuit in which stabilization of the lamp current is achieved via pulsewidth modulation (PWM) feedback control.

Yet, it is a seventh object of the invention to provide a CCFL controlcircuit in which constant frequency and frequency synchronization areimplemented to reduce frequency retardation interference within themulti-lamp circuit, caused by the use of different driving circuits.

Furthermore, it is an eighth object of the invention to provide a CCFLcontrol circuit in which constant frequency and phase synchronizationare implemented to reduce phase retardation interference within themulti-lamp circuit, caused by the use of different driving circuits.

Still, it is a ninth object of the invention to provide a CCFL controlcircuit in which the principal control elements can be fabricated on asame integrated circuit.

To provide a further understanding of the invention, the followingdetailed description illustrates embodiments and examples of theinvention, this detailed description being provided only forillustration of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings included herein provide a further understanding of theinvention. A brief introduction of the drawings is as follows:

FIG. 1 is a schematic view illustrating a traditional fixed frequencyoperation full bridge phase shift converter circuit;

FIG. 2A and FIG. 2B are time/sequence charts of the operation of thefixed frequency operation full bridge phase shift converter;

FIG. 3 is a schematic view illustrating a CCFL control integratedcircuit according to an embodiment of the invention;

FIG. 4 is a schematic view of a resonance network circuit according toan embodiment of the invention;

FIG. 5 is a schematic view illustrating a multi-lamp applying circuitaccording to an embodiment of the invention;

FIG. 6 is a schematic view illustrating the relationship between thecontrol signals of the control circuits according to an embodiment ofthe invention;

FIG. 7A and FIG. 7B are two schematic view illustrating two lamp currentphase configurations under similar frequency operation of multi-lampsaccording to an embodiment of the invention;

FIG. 8A is a schematic view illustrating a triangular wave generatorcircuit according to an embodiment of the invention;

FIG. 8B is a wave time/sequence chart corresponding to the circuit ofFIG. 8A; and

FIG. 9 is a schematic view of a phase synchronization ½ frequencydivider circuit according another embodiment of the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Wherever possible in the following description, like reference numeralswill refer to like elements and parts unless otherwise illustrated.

FIG. 3, FIG. 4, and FIG. 5 are schematic views respectively illustratinga cold cathode fluorescent lamp (CCFL) control circuit, a resonancenetwork circuit, and a multi-lamps applying circuit according to anembodiment of the invention. The multi-lamp LCD back-light controlcircuit of the invention uses a constant operating frequency and PWM(pulse width modulation) feedback to control the CCFL current.

As shown in FIG. 3, the multi-lamp LCD back-light control circuitcomprises full bridge switches 317, 318, 319, 320. The resonance networkcircuit 321, comprised of a step-up transformer 324, inductor 322, andcapacitors 323, 326, converts a direct current (DC) from a power source335 to an alternating current (AC) needed by the CCFL circuit 325. Theinductor 322 and capacitors 323, 326 of the resonance network circuit321 can be disposed on a primary side of the transformer as shown inFIG. 3, or on secondary sides 403, 404 of the transformer as shown inthe resonance network circuit 405 of FIG. 4. The inductors 322, 403 ofthe resonance network circuits 321, 405 as described above may be eitherindependent elements separate from the transformer, or leakage inductorsgenerated by the transformer. Similarly, the secondary side capacitor ofthe resonance network circuits 321, 405 can be either independentelectric clement or parasitic capacitor generated between the CCFL andthe LCD.

Among the full bridge switches, the switches 317, 320 connected to thepower source 335 (also called “power switches”) are PMOSFET switches,while the switches 318, 319 connected to the ground (also called “groundswitches”) are NMOSFET switches. Within the full bridge switches, thechange and output of the duty cycle of the switches 317, 320 arecontrolled via a PWM controller 302. In turn, the duty cycle of theswitches 318, 319 is constant and further must be controllable above50%. Furthermore, the phase relationship between the control signal ofthe NMOSFET ground switches 318, 319 and the control signal of thePMOSFET power switches 317, 320 is invariant. More particularly withrespect to the above NMOSFET and PMOSFET having a common drainconnection, when said NMOSFET is turned on, said PMOSFET is oppositelyturned off. With respect to the NMOSFET and PMOSFET without common drainconnection, said PMOSFET is turned on only after a preset delay afterthe turn on of the NMOSFET.

A triangular wave generator 336 is further connected to an input of thePWM controller 302. The operating frequency of the triangular wavegenerator 336 can be controlled through an external synchronous signaldelivered through a control terminal FSYN. A ½ divider circuit 306 isfurther used to generate a time sequence as driving input of the groundswitches 318, 319. The phase of the ½ divider circuit 306 can besynchronized via an external synchronous signal delivered through thecontrol terminal PSYN.

Referring to FIG. 5, the multi-lamps applying circuit is formed viacoupling between one another a plurality of integrated circuits (IC)501, 502, 503, each of which is respectively formed by assembly of thecontrol unit 301 as shown in FIG. 3. The ICs 501, 502, 503 usually havetheir respective frequency synchronous signal control terminal 504, 505,506 connected together so that all the ICs are operated with a samefrequency. Similarly, respective phase synchronous signal controlterminals 507, 508, 509 of the ICs may be connected together to operateall the ICs with a same phase.

With reference to FIG. 3 in conjunction with FIG. 6, now is describedthe relationship of the control signals between the CCFL control circuitand each control circuit. As illustrated, the CCFL control circuit ofthe invention is therefore provided with traditional full bridge switchstructures and traditional elements of a PWM controller to control theswitch of the CCFL and the lamp currents in a feedback control manner.In addition, NMOSFET and PMOSFET are used as switch elements to achievea more effective switching operation, which favorably increases theefficiency of the whole circuit. Furthermore, the CCFL control circuitof the invention includes different ICs that are connected to oneanother in such a manner that their respective operating frequency andphase can be synchronously controlled, thereby the perturbations due tofrequency and phase differences are prevented during the operation ofthe lamps.

Within the CCFL control circuit as shown in FIG. 3, the control unit 301comprises a PWM controller 302, a triangular wave/clock generator 336, a½ frequency divider 306, and a logic circuit. The PWM feedback controlcircuit typically measures the AC output 346 of the lamp 325. After ACfrom the lamp 325 is commutated and filtered through the feedbacknetwork 347, the resulting DC is delivered to the inverter input INN ofthe error amplifier 303 within the PWM controller 302 to be comparedwith a reference voltage VREF inputted to the not-inverter input INP.

The triangular generator 336 generates a triangular wave output 344which configuration is shown in FIG. 6 as reference numeral 601. Thevoltage level (reference numeral 602 in FIG. 6) of the output 345 of theerror amplifier 303 is compared with the triangular wave output 344 bymeans of a comparator 304 to obtain a PWM output wave (reference numeral603 in FIG. 6) at the output terminal 341. According to the currentintensity of the lamp 325, the PWM feedback control circuit cantypically modify the voltage level 602 at the output 345 of the erroramplifier 303 along which the duty cycle of the output wave 603 from thecomparator 304 is also changed. The output of the lamp 325 is therebyautomatically regulated.

The full bridge circuit of the invention hence is driven via drivingsignals, formed from a set of constant duty cycles greater than 50%,that are further accompanied with the output of the PWM controllergenerating an appropriate change of the duty cycle. In the invention,the control signals of constant cycles drive the NMOSFET 318, 319 asdescribed below.

By means of the ½ frequency divider 306, the clock triangular signal 601from the triangular wave generator is transformed to a clock signal 604(also called “half clock signal”) having a frequency equal to half thefrequency of the triangular signal 601. The inverter 334 then invertsthe half clock signal 604 to an inverted half clock signal 605. Bothclock signals 604, 605 are delivered through outputs 339, 340 to delays312, 311 and OR logic 316, 315 to generate signals 606, 608 of dutycycle greater than 50%, delivered through the outputs NOUT1, NOUT2. Thesignals 606, 608 have a duty cycle that is delayed a delay time 610behind the half clock signals 604, 605. If needed, this delay time canbe adjusted by means of a time delay controller element 333.

To drive the full bridge switches, the changed duty cycle from the PWMcontroller is combined with the driving signals of constant cycle in themanner described hereafter. A Boolean AND is applied to the half clocksignals 340, 339 and the output 341 of the PWM controller 302 by meansof the AND logic 307, 308, so that the PWM output 341 is in outputtingconfiguration only when the half clock signals are in the logic state“1”. The time delays of the delays 309, 310 can be controlled via thecontroller elements 333. AND logic 348, 349 enable the PWM output 341 tobe turned on only after a delay time 611 behind the turn on of theNMOSFET. Because the PMOSFET and NMOSFET respectively are driven via lowand high voltages, inverters 313, 314 therefore invert the PWM output toinfer the PMOSFET. Within the above circuitry, the control signal 607driving the PMOSFET 320 at the output POUT2 is in turn-on state (logic“0”) only if the control signal 606 driving the NMOSFET 318 at theoutput NOUT1 is in turn-on state (logic “1”). Similarly, the controlsignal 609 driving the PMOSFET 317 at the output POUT1 is in turn-onstate (logic “0”) only if the control signal 608 driving the NMOSFET 319at the output NOUT2 is in turn-on state (logic “1”).

As described above, another characteristic of the invention is asynchronous operation of the frequency and phase. As shown in FIG. 3,the oscillating frequency of the triangular wave generator 336 can besynchronized by means of externally added signals. Processing of thephase synchronous signals is included in the frequency divider circuit306. As shown in FIG. 5, while operating a plurality of lamps, all thenon-inverter input terminals 510, 511, 512 of the error amplifier areconnected to a same reference voltage 515 so that the current of thelamps are balanced. Meanwhile, by coupling all the frequency inputs 504,505, 506 of the controller ICs to one another in a synchronizingconfiguration, the lamps can be operated with a same frequency.Similarly, by coupling all the phase inputs 504, 505, 506 to one anotherin a synchronizing configuration, the lamps can be operated with a samephase. The requisite condition of operation with a same phase is thatthe circuitry must be operated with a same frequency. To obtain a highlyeffective operation of the circuitry, the operating frequency of thecontroller ICs can be chosen higher than the resonance frequency of theresonance network.

FIG. 7A and FIG. 7B schematically illustrate two possible phasevariations of the lamp current in an operation of multiple lamps with asame frequency. More particularly, FIG. 7A illustrates a lamp currentphase in inversion configuration within an operation of multiple lampswith a same frequency. FIG. 7B illustrates a lamp current phase insimilar configuration within an operation of multiple lamps with a samefrequency. When the phases are inverted, the flow of AC currents throughthe strayed capacitors between the lamps may generate current leakage.Via synchronous regulation, the invention favorably eliminates theoccurrence of current leakage and increases the performance of theentire circuit.

FIG. 8A is a schematic view of the triangular wave generator circuit,and FIG. 8B is a corresponding time/sequence chart. As shown in FIG. 8A,the triangular generator circuit 801 includes a raising edge detectorcircuit 802. It should be noted that the traditional triangular wavegenerator without synchronous function has the output 811 of thecomparator 810 short-circuited with the input 813 of the NAND gate 814.However, in the embodiment of the invention, a NMOSFET 804 with opendrain is added to synchronize the triangular generator with the externalsignal FSYN. If the connection scheme of the NMOSFET 804 and theexternal pull-up capacitor 805 is as shown in FIG. 5, a wired NOR logicthen is formed from NMOSFET 804, 815 of different ICs, the inverter 803then can change this NOR logic into an OR logic.

The raising edge detector circuit 802 further includes an AND gate 812which inputs are connected to the output 505 of the comparator 810 andthe output 815 of the raising edge detector circuit 802. The output 813of the AND gate 812 is inputted to the NAND gate 814 to control theoperation of the triangular generator. FIG. 8B is a time/sequence of theentire circuit according to an embodiment of the invention. In FIG. 8B,reference numeral 807 is the external synchronous control triangularsignal taken at the point A of FIG. 8A. Reference numeral 808 is theexternal synchronous control signal. Reference numeral 809 is theexternal synchronous control signal received by the triangular wavegenerator clock.

FIG. 9 schematically illustrates a phase synchronous ½ frequency dividercircuit according to an embodiment of the invention. As illustrated, toachieve a phase synchronous ½ frequency divider circuit, a common ½divider circuit 902 is further provided with a D-type inverser 902 thathas an output QN directly connected to the input D. Hence, if the phasesynchronous terminal PSYN of different IC are connected to one anotherand further to the Pull up capacitor 907, as traditionally achieved andillustrated in FIG. 5, a wired NOR is formed from NMOSFET 906, 908 ofdifferent ICs with a Pull up capacitor 907. The inverter 904 thusinverts the result of the NOR to an OR. When the entire circuit isoperated with a same operating frequency, the phase of the output CLK/2is therefore decided by the first IC switching to a logic state “1”(high level.

It should be apparent to those skilled in the art that the abovedescription is only illustrative of specific embodiments and examples ofthe invention. The invention should therefore cover variousmodifications and variations made to the herein-described structure andoperations of the invention, provided they fall within the scope of theinvention as defined in the following appended claims.

1. A multi-lamps liquid crystal display (LCD) panel back-light controlcircuit, comprising a control unit, an full bridge switch, a resonancenetwork circuit, a voltage transformer, a lamp, and a feedback network,wherein a constant operating frequency and a pulse width modulation(PWM) feedback are used to control a current of cold cathode fluorescentlamps (CCFL) (CCFLs), the back-light control circuit being characterizedin that a power switch of the full bridge switch outputs a duty cyclethat is controlled and changed via a PWM controller of the control unit,while a ground switch of the full bridge switch outputs a constant dutycycle controllable above 50%; wherein a phase relationship between asignal that controls the ground switch and a signal that controls thepower switch is constant, the ground switch being formed from at least aan NMOSFET and the power switch being formed at least from a PMOSFET;wherein with a common drain connection of the ground switch and thepower switch, the power switch is turned off when the ground switch isturned on, and without a common drain connection, the power switch isturned on only after a preset delay from a turn on of the ground switch.2. The circuit of claim 1, wherein the power switch of the full bridgeis formed from two PMOSFET PMOSFETs and the ground switch is formed fromtwo NMOSFET NMOSFETs.
 3. The circuit of claim 1, wherein the controlunit further comprises a PWM controller, a triangular wave/clockgenerator, a ½ frequency divider, and a logic circuit.
 4. The circuit ofclaim 3, wherein the PWM controller includes an error amplifier whichhas an output with a voltage level that is compared to an outputtedtriangular wave via a comparator before obtaining a PWM output wave. 5.The circuit of claim 3, wherein the ½ frequency divider transforms theclock of the triangular wave/clock generator to a half frequency clocksignal with a frequency equal to a half of the triangular wave, the aninverter inverting the half frequency clock signal to an inverted halffrequency clock signal; the half clock signal and the inverted halfclock signal being outputted through a delay and an OR logic to generatean output signal having a duty cycle greater than 50% and delayed fromthe half clock signal, wherein the delay time is adjustable by means ofa delay time controller element.
 6. The circuit of claim 3, wherein achanged duty cycle output generated from the PWM controller iscalculated as the result of an AND logic from the half clock signal andthe output of the PWM controller, thereby the output of the PWMcontroller is in an outputting state only when the half clock signal isin a “1” logic state, the delay being adjustable by means of controllerelements, and the AND logic enables the output of the PWM controller tobe turned on only after a delay from the a turn on of the NMOSFET;wherein the PMOSFET being of low driving voltage and the NMOSFET beingof high driving voltage, the inverter and the logic transform the PWMoutput to push the PMOSFET.
 7. The circuit of claim 3, wherein theoperating frequency and the synchronization of the operating phase ofthe triangular wave generator and the 1/2 divider circuit 1/2 frequencydivider are controlled via a plurality of external synchronous signalsdelivered through control terminals thereof.
 8. The circuit of claim 1or 3, wherein different integrated circuits are respectively formed fromthe control unit, the different integrated circuits (IC) includingeither a plurality of respective frequency synchronous signal controlterminals or a plurality of phase synchronous signal control terminalsthat are connected to one another so that the different ICs operaterespectively either with a same operating frequency or a same phase. 9.The circuit of claim 1, wherein the resonance network circuit includesan inductor and a capacitor that are placed in the voltage transformereither in a primary side or a secondary side.
 10. The circuit of claim 1or 9, wherein the inductor of the resonance network circuit is either aseparate and independent element from the voltage transformer or aleakage inductor generated by the voltage transformer.
 11. The circuitof claim 1 or 9, wherein the a secondary capacitor of the resonancenetwork circuit is either an independent element or a parasiticcapacitor generated between the CCFL CCFLs and the LCD display panel.12. A back-light control circuit for a liquid crystal display (LCD)panel, comprising: a lamp; a resonance network circuit; a feedbacknetwork commutating and filtering an AC output from the lamp; a fullbridge switch comprising a plurality of first switches connected to avoltage line and a plurality of second switches connected to a ground,the first and the second switches forming three conduction paths; and acontrol unit which controls the first switches to output a larger than50 % duty cycle and controls the second switches to output a less than50 % duty cycle in order to enable a current flows through one switch ofeach of the first and the second switches alternately, wherein aconstant operating frequency and a pulse width modulation feedback areused to control a current of the lamp, and the control unit comprises: aPWM (pulse width modulation) controller that controls and changes theduty cycles; and a triangular wave/clock generator, a logic circuit, anda 1/2 frequency divider which transforms a clock of the triangularwave/clock generator to a half frequency clock signal with a frequencyequal to a half of the triangular wave, an inverter inverting the halffrequency clock signal to an inverted half frequency clock signal, thehalf clock signal and the inverted half clock signal being outputtedthrough a delay and an OR logic to generate an output signal having aduty cycle greater than 50 % and delayed from the half clock signal,wherein the delay time is adjustable by means of a delay time controllerelement, and with a common drain connection of the second switches andthe first switches, the first switches are turned off when the secondswitches are turned on, and without a common drain connection, the firstswitches are turned on only after a preset delay from a turn on of thesecond switches.
 13. The circuit of claim 12, wherein the first switchesare PMOSFET switches and the second switches are NMOSFET switches. 14.The circuit of claim 12, wherein a phase relationship between a signalthat controls the second switches and a signal that controls the firstswitches is constant.
 15. The circuit of claim 12, wherein the PWMcontroller further includes an error amplifier which has an output witha voltage level that is compared to an outputted triangular wave via acomparator before obtaining a PWM output wave.
 16. The circuit of claim12, wherein a constant operating frequency and a pulse width modulationfeedback are used to control a current of cold cathode fluorescentlamps, wherein the operating frequency and a synchronization of anoperating phase of the triangular wave/clock generator and the 1/2frequency divider are controlled via an external synchronous signaldelivered through a terminal thereof.
 17. A back-light control circuitfor a liquid crystal display (LCD) panel, comprising: a lamp; aresonance network circuit; a feedback network commutating and filteringan AC output from the lamp; a full bridge switch comprising a pluralityof first switches connected to a voltage line and a plurality of secondswitches connected to a ground, the first and the second switchesforming three conduction paths; and a control unit which controls thefirst switches to output a larger than 50 % duty cycle and controls thesecond switches to output a less than 50 % duty cycle in order to enablea current flows through one switch of each of the first and the secondswitches alternately, wherein a constant operating frequency and a pulsewidth modulation feedback are used to control a current of the lamp, anddifferent integrated circuits (ICs) are respectively formed from thecontrol unit, each of the different integrated circuits including eithera plurality of respective frequency synchronous signal control terminalsor a plurality of phase synchronous signal control terminals that areconnected to one another so that the different ICs operate respectivelyeither with a same operating frequency or a same phase.
 18. The circuitof claim 17, wherein the resonance network circuit comprises a voltagetransformer, an inductor and a capacitor, wherein the inductor and thecapacitor are placed in a primary side or a secondary side of thevoltage transformer.
 19. The circuit of claim 18, wherein the inductorof the resonance network circuit is an inductor selected from a groupconsisting of a separate and independent element from the transformerand a leakage inductor generated by the voltage transformer.
 20. Thecircuit of claim 19, wherein a secondary capacitor of the resonancenetwork circuit is either an independent element or a parasiticcapacitor generated between a CCFL and the LCD panel.